SAMSUNG Internship Opportunity at Chennai. Interested Candidates can go through the details and apply using the link provided at the bottom of the Post.
About SAMSUNG
Samsung is a South Korean multinational conglomerate that produces a wide range of electronic devices, including smartphones, televisions, laptops, and home appliances. Founded in 1938 by Lee Byung-chul, Samsung has grown to become one of the world’s largest and most recognizable technology brands, with a strong focus on innovation and quality. Samsung has also invested heavily in research and development, enabling it to stay at the forefront of technological advancements. In addition to its consumer electronics division, Samsung also has interests in other areas such as construction, finance, and biotechnology.
SAMSUNG Recruitment 2023
| Company name | SAMSUNG |
| Website | www.samsung.com |
| Job Role | Physical Design Engineer |
| Work Location | Bangalore, India |
| Job Type | Full Time |
| Experience | Freshers are Eligible |
| Qualification | Graduate (Any Discipline) |
| Batch | 2023 |
| Package | 11 – 14 LPA(Estimated) |
Job Description
Samsung is currently seeking candidates for the position of Physical Design Engineer.
Candidate Responsibilities:
- Contribute to the intricate SOC Top Physical Implementation for next-generation SOCs, focusing on mobile application processors, modem sub-systems, and connectivity chips. This involves tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs.
- Act as a proficient user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and comprehend their functionalities.
Candidate Requirements:
- Graduate in any discipline.
- Fresh graduates are welcome to apply.
- Experience with large SOC designs (>20M gates) operating at frequencies over 1GHz.
- Expertise in block-level and full-chip SDC clean-up, Synthesis optimization, Low Power checking, and logic equivalence checking.
- Familiarity with deep sub-micron designs (8nm/5nm) and associated challenges (manufacturability, power, signal integrity, scaling).
- Understanding of typical SOC issues, including multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and package interactions.
- Knowledge of hierarchical design, top-down design, budgeting, timing, and physical convergence.
- Good understanding of the Physical Design Verification methodology to diagnose LVS/DRC issues at the chip/block level.
- Experience with recent successful SOC tape-outs.
How to Apply?
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- Enter your personal details and any other information requested by the company in the application portal.
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- Ensure that your contact information is correct and up-to-date, and accurately reflect your qualifications and experience.
- Submitting an application with incorrect or incomplete information could harm your chances of being selected for an interview.
Apply before the Job is filled.
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